Dev Tools · 4h ago
First CHERIoT Chip Tapes Out, Boosts IoT Memory Safety
The first silicon implementation of the CHERIoT architecture has been fabricated, bringing hardware-enforced memory safety to low-cost IoT devices. CHERIoT extends the CHERI capability model to microcontrollers, preventing common memory bugs without software overhead. The chip, built on a 28nm process, targets secure embedded systems and edge computing applications.
Meridian48 take
While promising, the real test will be adoption: CHERIoT needs broad industry buy-in to displace decades of unsafe C code in firmware.
memory-safetyiot-security